1. Field of the Invention
The present invention relates to an array substrate for a fringe field switching (FFS) mode liquid crystal display (LCD) device, and more particularly, to an array substrate for an FFS mode LCD device capable of preventing a wavy noise problem and a photo leakage current problem. The FFS mode LCD device yields reduced production costs. There is also a method of fabricating the array substrate.
2. Discussion of the Related Art
A related art liquid crystal display (LCD) device uses optical anisotropy and polarization properties of liquid crystal molecules. The liquid crystal molecules have a definite alignment direction as a result of their thin and long shapes. The alignment direction of the liquid crystal molecules can be controlled by application of an electric field across the liquid crystal molecules. As the intensity or direction of the electric field is changed, the alignment of the liquid crystal molecules also changes. Since incident light is refracted based on the orientation of the liquid crystal molecules due to the optical anisotropy of the liquid crystal molecules, images can be displayed by controlling light transmissivity.
Since the LCD device including a thin film transistor (TFT) as a switching element, referred to as an active matrix LCD (AM-LCD) device, has excellent characteristics such as high resolution and display of moving images, the AM-LCD device has been widely used.
The AM-LCD device includes an array substrate, a color filter substrate and a liquid crystal layer interposed therebetween. The array substrate may include a pixel electrode and TFT, and the color filter substrate may include a color filter layer and a common electrode. The AM-LCD device is driven by an electric field between the pixel electrode and the common electrode resulting in excellent properties of transmittance and aperture ratio. However, since the AM-LCD device uses a vertical electric field, the AM-LCD device has a bad viewing angle.
An in-plane switching (IPS) mode LCD device may be used to resolve the above-mentioned limitations. FIG. 1 is a cross-sectional view of an IPS mode LCD device according to the related art. As shown in FIG. 1, the array substrate and the color filter substrate are separated and face each other. The array substrate includes a first substrate 10, a common electrode 17 and a pixel electrode 30. Though not shown, the array substrate may include a TFT, a gate line, a data line, for example. The color filter substrate includes a second substrate 9, a color filter layer (not shown), for example. A liquid crystal layer 11 is interposed between the first substrate 10 and the second substrate 9. Since the common electrode 17 and the pixel electrode 30 are formed on the first substrate 10 on the same level, a horizontal electric field “L” is generated between the common and pixel electrodes 17 and 30.
FIGS. 2A and 2B are cross-sectional views showing turned on/off conditions of an IPS mode LCD device according to the related art. As shown in FIG. 2A, when the voltage is applied to the IPS mode LCD device, liquid crystal molecules 11a above the common electrode 17 and the pixel electrode 30 are unchanged. But, liquid crystal molecules 11b between the common electrode 17 and the pixel electrode 30 are horizontally arranged due to the horizontal electric field “L”. Since the liquid crystal molecules are arranged by the horizontal electric field, the IPS mode LCD device has a characteristic of a wide viewing angle. FIG. 2B shows a condition when the voltage is not applied to the IPS mode LCD device. Because an electric field is not generated between the common and pixel electrodes 17 and 30, the arrangement of liquid crystal molecules 11 is not changed. However, the IPS mode LCD device has poor aperture ratio and transmittance.
A fringe field switching (FFS) mode LCD device has been introduced to resolve the above-mentioned limitations. FIG. 3 is a cross-sectional view of an array substrate for an FFS mode LCD device according to the related art. As shown in FIG. 3, an array substrate includes a substrate 41, a gate line (not shown), a data line (not shown), a thin film transistor (TFT) “Tr”, a common electrode 44 and a pixel electrode 69. The gate line (not shown) and the data line (not shown) are formed on the substrate 41 and cross each other to define a pixel region P. The gate line (not shown) is insulated from the data line (not shown) due to a gate insulating layer 49. The TFT “Tr” is formed at a crossing portion, which is defined as a switching region “TrA”, of the gate line (not shown) and the data line (not shown). The TFT “Tr” includes a gate electrode 46, a semiconductor layer 57 including an active layer 53 and an ohmic contact layer 55, a source electrode 60 and a drain electrode 62. The gate electrode 46 is connected to the gate line (not shown), and the source electrode 60 is connected to the data line (not shown).
A passivation layer 65 is formed to cover an entire surface of the substrate 41 and be disposed over the TFT “Tr”. The passivation layer 65 has a drain contact hole 67 to expose a portion of the drain electrode 62. A plurality of pixel electrodes 69 are formed on the passivation layer 65 and spaced apart from each other. The pixel electrodes 69 are connected to the drain electrode 62 through the drain contact hole 67. In addition, a common electrode 44 having a plate shape is formed on the substrate 41 and under the gate insulating layer 44. When voltages are applied to the common electrode 44 and the pixel electrodes 69, a fringe field is induced to control liquid crystal molecules (not shown). Although the common electrode 44 and the pixel electrodes 69 are formed in the pixel region “P”, aperture ratio and transmittance are not reduced because they are formed of a transparent conductive material.
The array substrate for the FFS mode LCD device is fabricated through five or six mask process. Among these processes, the five mask process is used to reduce production costs. The array substrate in FIG. 3 is formed by a five mask process. In the five mask process, the source and drain electrodes 60 and 62 and the semiconductor layer 57 are patterned by a single mask process using a diffractive mask or a half-tone mask. As a result, the semiconductor layer 57, especially the active layer 53, protrude beyond the source and drain electrodes 60 and 62 such that both ends of the active layer 53 are not covered with the source and drain electrodes 60 and 62, as an “A” region. Although not shown, since the data line (not shown) is formed by the same mask process as the source electrode 60, a semiconductor pattern extending from the semiconductor layer 57 is formed under the data line (not shown). Similar to the semiconductor layer 57, the semiconductor pattern (not shown) protrudes beyond the data line (not shown) such that both ends of the semiconductor pattern (not shown) are not covered with the data line (not shown).
Because the active layer 53 of the first semiconductor layer 57 is formed of amorphous silicon, a photo leakage current is generated due to light from the backlight unit or ambient light. As a result, properties of the TFT “Tr” are degraded due to the photo leakage current. Moreover, because the active layer of the semiconductor pattern (not shown) under the data line (not shown) is also formed of amorphous silicon, a leakage current is also generated in the semiconductor pattern (not shown) due to ambient light. The light leakage current causes a coupling of signals in the data line (not shown) and the pixel electrode 69 to deteriorate, resulting in a wavy noise phenomenon when displaying images. A black matrix (not shown) designed to cover the protruding portion of the semiconductor pattern (not shown) reduces aperture ratio of the LCD device.